An erasable, programmable, read-only memory (EPROM) provides non-volatile storage that can be erased and rewritten, albeit in a special write/erase operation that takes considerably longer than the normal read cycle. EPROMs are typically fabricated with an array of bit-cells, each with an electrically isolated, floating gate that can be selectively charged. Thus, each bit-cell can assume either of two logic states (1 or 0), depending upon whether the floating gate is charged.
Two principal mechanisms are used to provide the erasability feature of EPROMs--ultraviolet light (UV-EPROM) and low current electrical tunnelling (EEPROM). For UV-EPROMs, ultraviolet light is directed onto an entire bit-cell array, causing charge neutralization in each floating gate that is in the charged logic state. For EEPROMs, the floating gate for each bit-cell can be individually erased (discharged) using low current electrical tunneling.
For either type of EPROM, write/erase operations (logic state 1) are considerably more destructive of bit-cell integrity than is a read operation. Bit-cell degradation does not necessarily lead to bit-cell failure during the write/erase operations, so that a fatally damaged bit cell cannot necessarily be detected by an immediate read operation. Accordingly, the number of write/erase cycles before bit-cell failure is the limiting factor in determining endurance and reliability for an EPROM. Moreover, since these bit-cell failures occur randomly throughout the bit-cell array, and occur for both logic state 1 and logic state 0 bit cells, reliability considerations require a memory replacement cycle that takes into account a worst-case write/erase cycle specification to avoid data loss from bit-cell failure.
For example, in the case of EEPROMs, typical endurance specifications are on the order of ten thousand write/erase cycles for any bit-cell. While many applications for EEPROMs do not require a significant number of write/erase cycles, EEPROMs in particular are being used in an increasing variety of microcontroller-type applications (such as in the automotive and telecommunications fields) where the EEPROM program is, continually updated, and the EEPROM is used to store not only program instructions but also parameters and other variable data that are also regularly modified.
The most common technique for compensating for bit-cell failures in EPROMs is to provide worst-case and/or MTBF (mean time between failure) endurance specifications. While endurance specifications provide a measure of reliability, they do not correct or compensate for bit-cell failures. Moreover, they lead to a worst-case replacement cycle for the EPROMs.
Recently, redundant-bit-bit-cell EEPROMs have become available. The Q-Cell EEPROM, available from Seeq, Inc. San Jose, CA, provides two redundant bit-cell arrays. To correct for bit-cell failure, the Q-Cell includes circuitry for comparing the redundant data bits read from corresponding redundant bit-cells according to a logical OR function--in terms of exemplary logic states, if either or both of the redundant data bits from corresponding redundant bit-cells is a logic state 1, then the Q-cell provides a logic state 1 output data bit (a logic state 0 output data bit is provided only when both redundant data bits are logic state 0). That is, in terms of the exemplary logic states, the Q-Cell technique for correcting bit-cell failures assumes that a bit-cell that fails always appears to be in the logic state 0.
The practical disadvantage of a dual-bit redundancy technique for correcting bit-cell failures is that failures can occur in bit-cells that are in either state 1 or 0, i.e., the floating gate for a bit-cell can become either inadvertently charged or discharged. While manufacturing processes can be adjusted to make inadvertent, floating gate discharge more likely than inadvertent floating gate charge, nevertheless, the inability to correct failures in logic state 0 bit cells reduces the advantages of the dual-bit redundancy technique for correcting bit-cell failures. Moreover, none of the current redundant-bit-cell memories provide any notification of a bit-cell failure that has occurred.
Another technique for correcting, or at least detecting, bit-cell failures is through the use of parity, error-checking or error-correcting bits stored along with data bytes in a memory. While parity and error checking/correcting schemes are commonly used in RAM memories, their use in EPROMs is problematic. While EPROMs are typically read on a byte basis, write/erase operations are performed on a bit basis so that only a minimum number of bit-cells are affected during each write/erase operation. Incorporating parity or error checking/correcting bits would require those bits to be changed during nearly every write/erase cycle, so that these bits would then become the limiting factor in EPROM endurance and reliability. Moreover, during a byte programming operation, individual bits are either set to 1 or set to 0, so that a byte containing parity or error checking/correcting bits would almost always require both programming operations for any byte modification.
Accordingly, a need exists for an EPROM that includes the capabilities of detecting bit-cell failures and providing an error-flag notification of such failures.